1. Field of the Invention
This invention relates to a current mirror circuit and, more particularly, to a current mirror circuit suitable for a wide range input current and low voltage integrated circuit.
2. Description of the Prior Art
Current mirror circuits are well known in the art as a means for supplying a known current as, for example, in biasing transistor gain stages. While a "current source" may be as simple as a resistor, current mirrors have become increasingly used for several reasons. First, they offer improved circuit performance and more accurate current control than do resistors, and also require less area on an integrated circuit chip. The most conventional and simple circuit for a current mirrors requires high beta (beta means an amplifying coefficient and refers as .beta.) transistors, or at least transistors having consistent values of .beta., in order to approach the desired corelation between output and reference or input current. In IC (integrated circuit) processing, this is, of course, difficult and thus expensive as .beta. values tend to have a wide range of values and restriction of the usable range of values makes for a low IC production yield.
FIGS. 1 to 2 show schematic diagrams of typical prior art current mirror circuits. Throughout the drawings, like reference numerals and letters are used to designate like or equivalent elements for the sake of simplicity of explanation.
FIG. 1 shows the proto-type current mirror circuit which has PNP transistors Q1 and Q2 with their base-emitter paths connected in parallel to a power supply line 11 supplied with a power source voltage Vcc therefrom. Transistors Q1 is connected in the diode-fashion by itself and at its collector to an input current source 12. An output current Iout is derived from the collector of transistor Q2.
However, this circuit arrangement has a drawback in that an error of a comparatively large magnitude is provided between an input current Iin supplied by input current source 12 and output current Iout due to the base current of transistors Q1 and Q2. Since there arise some bad influences such as an error between base currents Ib1 and Ib2 of transistors Q1 and Q2, and more the so-called Early effect. A relation between output current Iout and input current Iin is, therefore, given as follows when the influences of the error between base currents Ib1 and Ib2 and the Early effect are considered; ##EQU1## where Vce1 and Vce2 designate the voltage drops across the collector-emitter pathes of respective transistor Q1 and Q2, Va designates the Early voltage of bipolar transistors.
FIG. 2 shows an improved prior art current mirror circuit. This circuit comprises a differential circuit 15 comprised of emitter-coupled NPN transistors Q3 and Q4 in addition to current mirror PNP transistors Q1 and Q2. Transistor Q3 has its collector connected to a power supply source 11 and its base connected to the collector of transistor Q1. On the other hand, transistor Q4 has its collector connected to the bases of transistors Q1 and Q2 and its base connected to a reference voltage source 13 of reference voltage Vref. The emitters of transistors Q3 and Q4 are connected through a current source 14 of current value Ics to a circuit ground GND. Current Ics is set to be higher than the sum of base currents Ib1 and Ib2 of transistors Q1 and Q2, i.e., Ics&gt;Ib1+Ib2. Transistor Q3 is provided for the level shift, and thus potential Vb3 at the base of transistor Q3 is determined by reference voltage Vref. Namely, the circuit of FIG. 2 can be operated from a low supply voltage so long as reference voltage Vref has such a magnitude to render all the transistors conductive.
In the circuit of FIG. 2, both the bases of transistors Q1 and Q2 are kept in almost the same potential. Collector-emitter voltages Vce1 and Vce2 of transistors Q1 and Q2, therefore, balance each other if reference voltage Vref is made equivalent with the collector potential of transistor Q2. Accordingly, the influence of the Early effect in the pair of transistors Q1 and Q2 can be illuminated. And further, the influence of the Early effect in the pair of transistors Q3 and Q4 can be also disregarded since the Early voltage Va(NPN) for NPN ransistors is very large enough to ignore results of culculations Vce3/Va and Vce4/Va. Therefore, a relation between output current Iout and input current Iin in the circuit of FIG. 2 is presented as follows; ##EQU2## where .beta.n and .beta.p designate current amplification factors of NPN and PNP transistors respectively.
From the above equation (2), it is understood that an influence of the .beta.p is very small. On the other hand, current Ics of current source 14 is entered in the equation (2) as an error component. However the term Ics/(1+.beta.n) can also be ignored since .beta.n&gt;&gt;.beta.p and provided that current Ics is set in a prescribed value. Therefore, the circuit of FIG. 2 has been almost prevented from the bad influences from the error between base currents Ib1 and Ib2 of transistors Q1 and Q2 and the Early effect.
However, this circuit arrangement of FIG. 2 still has a drawback that current Ics of current source 14 is always required a relatively large value more than a prescribed value. That is, current Ics of current source 14 must be larger than the sum of base currents Ib1 and Ib2 of transistors Q1 and Q2, i.e., Ics&gt;Ib1+Ib2. In the event of input current Iin from input current source 12 being variable, current Ics is necessary to ensure the sum of the maximum values Ib1(max) and Ib2(max) of base currents Ib1 and Ib2. Therefore, the necessary amount of current Ics is determined as follows, i.e., Ics&gt;2Iin(max)/.beta.p, where Iin(max) designates the maximum value of input current Iin. Accordingly, a relative amount of current Ics is compensated in vain when input current Iin is small.
The circuit of FIG. 2 has also another drawback that the influence of the term Ics/(1+.beta.n) in the equation (2) becomes not ignored for the error between output current Iout and input current Iin when Iin&lt;&lt;Ics. The the circuit of FIG. 2 is still insufficient for the use wherein input current Iin is variable.